The fabrication of integrated chips can be broadly separated into two main sections, front-end-of-the-line (FEOL) fabrication and back-end-of-the-line (BEOL) fabrication. FEOL fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) within a semiconductor substrate. BEOL fabrication includes the formation of one or more metal interconnect layers comprised within one or more insulating dielectric layers disposed above the semiconductor substrate. The metal interconnect layers of the BEOL electrically connect individual devices of the FEOL to external pins of an integrated chip.
As the size of a semiconductor device size decreases, low dielectric constant (LK) materials and extra-low k (ELK) materials that have dielectric constants less than that of silicon dioxide have begun to be implemented in some designs as insulating materials between interconnects. However, a layer comprising LK materials or ELK materials may be damaged by a patterning process such as an etch process if it takes a long time to form a desired pattern. Accordingly, a need has developed in the art for an improved method of forming an interconnect structure for an integrated chip.